Tag Archives: verilog

Read Spartan6LX DNA Serial Number

Spartan6 Contain DNA logic — DNA_PORT, We can let this as random seed:) This is 57bits numbers. DNA_PORT DNA_PORT_inst(   .DOUT(dna_dout),   .CLK(dna_clk),   .DIN(1’b0),   .READ(dna_read),   .SHIFT(dna_shift) ); DNA_PORT is act as SPI Slave, capture at raise edge, … Continue reading

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Bug in data2mem…

I using data2mem to replace data in BlockRAM, It confused me when I try to replace BlockRAM data in Spartan6 Devices. There are correct in BRAM16 with 8bits and 16bits, only error BRAM18 with 18bits. Update: bug exist in ISE … Continue reading

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关于高层次综合

最近对高层次综合比较感兴趣,目前有一个需求是把一些算法或者控制用C来描述,然后再改写为Verilog。想抽空自己做高层次综合工具。 初步的打算是把自己写的CRC编码器转换为Verilog。而这个可以作为练手的东西。

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